This invention relates to a semiconductor device, and more particularly, to a sensing amplifier driving system, for example, techniques for providing the reading operation of SRAM (static random access memory) at high speed and low power-consumption, whereby a bit line and a common data line are precharged to a desired level.
In the conventional manner, one bit line of a complementary pair of bit lines is supplied with a power supply voltage, the other bit line is supplied with the ground potential of a circuit; each line is charged, and then the complementary bit lines are short-circuited to precharge both bit lines to the intermediate level by effecting a re-distribution of charges. Such techniques are found in the specifications of U.S. Ser. No. 860411, U.S. Ser. No. 943063, filed Dec. 18, 1986, and U.S. Ser. No. 60334.
However, the above precharging system of bit and common data lines requires two operational steps, that is, the operation to charge the complementary bit lines to the power supply voltage and the ground potential, respectively, and the succeeding operation to short-circuit the complementary bit lines. Moreover, in the precharging period, a waiting time for selection of word lines to write data is necessary so as to prevent writing error data into a memory cell. Therefore, not only is the timing for reading data complex, but there is a limitation of high-speed data read-out because of a longer access time. Such disadvantages are made clear by a careful reading of the present invention and as it relates to the disclosed embodiments.
For more high-speed operation, the specification of co-pending U.S. Ser. No. 148432, filed Jan. 26, 1988, describes another precharging system, where a pair of bit lines are precharged to the power supply voltage, and a pair of common data lines are precharged to the ground potential. In this system, however, the voltage of the common data lines changes from the ground voltage, so it is clear that data is difficult to be read with high speed. Japanese Patent Laid-open No. 63-58697 (published on the 14th of March, 1988) describes the system to select a common data line voltage using the voltage divided by resistors.